1. Technical Field
The present invention relates generally to sense amplifier circuits, and, more particularly, to sense amplifier circuits for use in memory arrays using transistor memory cells. More specifically, the present invention relates to a two mode sense amplifier for use in a memory array using either static RAM or dynamic RAM transistors that includes a latch for driving the output data.
2. Description of the Related Art
Sense amplifiers for use in memory arrays are well-known. A typical sense amplifier is used to detect low-level signals received from the cells within the memory array and convert the signals to levels compatible with the rest of the system in which the memory is used. As memory density increases, the memory cell size and the corresponding cell output signal is reduced, thereby making the sense amplifier critical for high-speed applications. The sense amplifier should be highly sensitive and still meet the speed requirements of the high-density memories.
A conventional sense amplifier detects the memory cell output through a differential amplifier, which is highly sensitive, but has very small voltage gain. The sense amplifier requires a biasing circuit that uses static power and is also supply voltage and process sensitive.
Separate latch circuits are also provided to hold the output data to drive the next stage. These additional circuits typically induce added delay in the sense amplifier.